1. Field of the Invention
The present invention relates to a semiconductor device having multilayer wiring, formed by stacking a number of wiring layers, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Various semiconductor devices having multilayer wiring are now available. In accordance with the development of the Silicon-On-Chip (SOC) technique, system LSIs, for example, which have various IP (Intellectual Property) devices, such as a memory, logic, analog circuit, etc., mounted on a single chip, have become available. SOC devices, such as system LSIs incorporating several types of IP device, are manufactured by very time-consuming, complicated processes. In particular, SOC devices having more than ten wiring layers are manufactured by an extremely complicated process. However, SOC products generally have a short life cycle. Therefore, it is very important to shorten the turnaround time (TAT) of the development of SOC products.
In the case of, for example, LSIs, in which semiconductor elements such as transistors are formed on a semiconductor substrate, and wiring layers are sequentially deposited on the resultant structure, about twenty days are needed to manufacture, by way of trial, a half-finished product in which transistors and a first wiring layer are provided on a semiconductor substrate (hereinafter referred to as an “underlayer”). Further, about five days are needed to form one wiring layer. To form ten wiring layers, for example, on the above-mentioned underlayer, about fifty days are needed. Accordingly, about seventy days are required to form a complete product including an underlayer with ten wiring layers.
As described above, the conventional semiconductor device manufacturing process, in particular, the process of manufacturing multilayer SOC products, is very complicated, and hence a lot of time is needed to develop a trial product (LOT) and/or manufacture such devices. In addition, the life cycle of SOC products is short, as previously mentioned, which makes it impractical to develop trial products using much time.